NormalComputing · Mountain View
Skills: Python, Accessibility
NORMAL COMPUTING | BUILD WITH US Normal is an applied AI company solving the hardest problems in AI and silicon. We build foundational hardware and software for the semiconductor industry, critical AI infrastructure, and the broader systems that power our world, in partnership with the world's most advanced institutions. We work as one team across New York City, Silicon Valley (Mountain View), London, Copenhagen, and Seoul. THE ROLE Normal is building AI inference hardware based on our revolutionary new Thermo In-Memory Computing architecture and as Memory Architect you will lead the translation of these concepts from theory into silicon. You will have free rein to completely reimagine each element of a conventional memory; from the design and layout read/write paths, organization of memory arrays, to the development of a microarchitecture which seamlessly interleaves core memory operations with high performance compute. Ultimately, you will be responsible for delivering 100-1000× improvements in performance in AI inference. You will report to the Director of Silicon Engineering and partner with scientists, microarchitects, physical design, and analog design engineers to implement a new standard cell library which combines existing digital compute primitives with Normal’s ThermoDRAM compute primitives. You will translate these new compute primitives into a highly performant Compute In-Memory System. You will own the technical relationship with major manufacturers from PDK acquisition through tapeout of test chips and production silicon. This role requires a seasoned engineer with prior experience in memory technology but who understands that radical performance improvements require radical paradigm shifts. WHAT YOU WILL OWN - Architecture for Processing-In-Memory: Define the memory requirements and floorplan that enable in-memory compute capability. This includes not only read/write paths to ALUs but also novel memory primitives. Specify the read/write circuitry row…
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