Analogue Insight · United Kingdom
Skills: Python
THE COMPANY Established in early 2024, at Analogue Insight we are bridging the Analogue and Digital Worlds for Tomorrow through our Chiplet Solutions. Our core expertise lies in developing cutting-edge Chiplet technology that serves as the building block for advanced communication systems. Our Chiplets are designed to offer high performance, scalability, and integration flexibility, enabling our clients to achieve breakthroughs in computation speed, data processing, and connectivity. For more information about us, check out our website (Analogue Insight) and LinkedIn Page (Analogue Insight™: Overview | LinkedIn).
THE ROLE We are seeking a talented and motivated Graduate Digital Design Engineer to join our team and contribute to the design and verification of digital and mixed-signal IP for our chiplet solutions, including PCS (Physical Coding Sublayer) logic and custom high-speed interfaces such as UCIe, Ethernet and PCIe. Working alongside experienced digital and analog engineers, you will write RTL, build testbenches and behavioural models, and see your work go into customer silicon. This role is well suited to recent graduates with a strong foundation in digital design who want to learn fast through hands-on work in a small, high-impact team. Hiring Manager:Christian Borelli, Founder and CSO.
KEY RESPONSIBILITIES
RTL Design: Design and implement digital blocks for PCS and interface IP (e.g. encoders/decoders, scramblers, PRBS generators/checkers, FIFOs, CDC logic, control and calibration state machines) in Verilog/SystemVerilog, under the guidance of senior designers. Standards & Specifications: Study SerDes and UCIe standards and architecture documents, and help turn them into clear block-level specifications. Verification: Build testbenches and run simulations to verify your designs, using SystemVerilog, UVM or cocotb, and help develop verification plans and coverage. Mixed-Signal Modelling: Write behavioural models of analog blocks in Verilog/Sys …truncated… nd h…
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