itd · Arizona
itD is seeking a DFT (Design For Test) Lead to drive the implementation and integration of advanced Design-for-Test (DFT) solutions across the silicon development lifecycle, ensuring highly testable, manufacturable, and reliable ASIC designs. The ideal candidate will bring deep expertise in ASIC DFT methodologies, post-silicon validation, and test architecture development, with a proven track record of delivering production-ready silicon through cross-functional collaboration. Location: Hybrid in Carlsbad, CA or Allentown, PA , or U.S. Remote . Candidates must be available to work Pacific Time business hours (9:00 AM–5:00 PM PST). Duration: 14 months We provide comprehensive medical benefits, a 401k plan, paid holidays, and more. Please note that we are only considering direct W2 candidates at this time, as we are unable to offer sponsorship. Responsibilities: Lead the implementation of hardware Design-for-Test (DFT) features, including scan, memory BIST (MBIST), BISR, boundary scan, and DFT simulation setup and debugging. Develop innovative DFT IP in collaboration with cross-functional engineering teams and integrate testability features into full-chip RTL designs. Drive reusable DFT and debug methodologies for next-generation silicon devices, including bare die and stacked die architectures. Perform post-silicon debugging, root cause analysis, and production qualification activities to improve silicon yield, reliability, and manufacturability. Collaborate with physical design, validation, and hardware engineering teams throughout the complete silicon product lifecycle. Design, validate, and release ATPG patterns while supporting manufacturing test readiness and production ramp. Develop technical solutions and resolve complex DFT challenges with minimal supervision while providing technical leadership to the broader engineering team. Internal Responsibilities: Attend regular internal practice community meetings. Collaborate with your itD practice team on industry t…
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