neuralink · South San Francisco, California, United States
Skills: Python
About Neuralink: We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world. About the Role We are seeking a Senior Physical Design Engineer to own block-to-full-chip implementation and signoff on advanced-node, multi-die 3DIC products. You will drive hierarchical physical design from RTL handoff through tapeout, and lead the multi-physics verification (thermal, mechanical/warpage, and IR/EM) that is unique to stacked-die and chiplet-based systems. This role sits at the intersection of traditional block-level signoff and the emerging discipline of 3D system-level closure. Key Responsibilities Hierarchical Physical Design Define and execute the hierarchical partitioning strategy: block boundaries, feedthroughs, pin placement, and budgeting across levels of hierarchy. Develop and maintain floorplans, power grids, and timing/physical budgets for large multi-block SoCs. Own the interface between block owners and top-level integration, including abstract (ILM/ETM) generation, boundary timing, and hierarchical ECO propagation. Manage die-to-die partitioning for 3D stacks – assign logic to tiers, plan hybrid-bond / µbump / TSV interfaces, and align inter-die floorplans. Block-level Implementation & Signoff Synthesis: Drive logic synthesis (constraints, DFT insertion, physical-aware synthesis), QoR analysis, and RTL-to-gate correlation. Floorplanning: Macro placement, power planning, congestion and timing feasibility, and pin/port optimization. Placement & Optimization: Standard-cell placement, timing-driven and congestion-driven optimization, useful-skew and multi-corner/multi-mode closure. CTS: Clock tree synthesis and clock distribution (including inter-die clocking for 3D), skew/latency balancing, and OCV/AOCV/POCV-aware clock closure. Routing: Detailed routing, DRC/LVS convergence, signal integrity (…
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