graphcore · Bristol, UK; Cambridge, UK; London, UK
Skills: Python
:pointer-events-auto R6Vx5WthreadScrollVars scroll-mb-calc(var(--scroll-root-safe-area-inset-bottom,0px)+var(--thread-response-height)) scroll-mt-calc(var(--header-height)+min(200px,max(70px,20svh)))" data-turn-id="request-WEB:0fbc0e63-7a29-4549-b136-67f3c3174a55-0" data-turn-id-container="request-WEB:0fbc0e63-7a29-4549-b136-67f3c3174a55-0" data-testid="conversation-turn-2" data-turn="assistant"> About the job Own verification that turns complex silicon architecture into reliable AI compute hardware. As a Silicon Verification Engineer, you will help ensure Graphcore RTL matches the architecture specification. Your work will protect silicon quality before designs move into physical implementation. You will sit where architecture, logical design and verification meet. You will directly influence how issues are found, understood and resolved before they become costly. You will plan verification, define coverage, generate tests and diagnose failures. You will also improve shared infrastructure that helps engineers move faster and identify problems earlier. The work is technically deep, with clear impact on our silicon. You will help build the discipline, pace and quality needed for ambitious AI compute programs at scale. The team and culture The verification team works closely with Architecture, Logical Design and Physical Design. Clear plans, coverage goals, test results and direct technical feedback shape the work. You will take ownership, follow evidence and keep communication open across sites. The team values people who speak up early and make complex problems easier to solve. Decisions are driven by technical reasoning, shared data and practical trade-offs. You will have room to lead through your expertise, not just your title. What we're looking for Verification experience in CPU, ASIC or closely related silicon environments Experience with UVM, SVA, assembly, compilers, Git or DRMS tools Ability to plan verification work and drive functional coverage to closure…
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