astspacemobile · Edinburgh, Scotland, United Kingdom
Skills: Python
AST SpaceMobile and our global partners are building the first and only space-based cellular broadband network to be accessible by standard smartphones. Called SpaceMobile, this ultra-powerful network is being designed to provide connectivity at 4G/5G speeds everywhere on the planet – on land, at sea and in flight. Position Overview We are seeking an ASIC Design Engineer to contribute to the design and implementation of complex silicon solutions used in AST’s space‑based communications systems. The Silicon Team in Edinburgh is a small, highly focused group responsible for developing high‑value silicon that is core to AST’s mission of “Connecting the unconnected” - delivering the world’s first space‑based mobile broadband network. The team works collaboratively to define and build next‑generation silicon, exploring advanced silicon technologies to continuously improve performance, capability, and efficiency. This is a hands‑on environment where silicon decisions directly impact AST’s ability to deliver a global communications network from space. In this role, you will focus on high‑quality RTL development, micro‑architecture definition, and close collaboration across engineering disciplines. You will work alongside architecture, verification, and system teams—both internal and external—to deliver robust, high‑performance ASIC and SoC designs from concept through tape‑out. Key Responsibilities: • Create high‑quality micro‑architecture specifications and RTL code. • Contribute to SoC integration and subsystem development. • Work with internal and external stakeholders, including architecture, verification, and software teams. • Participate in design reviews, providing technical input. • Ensure alignment with requirements and design best practices. Qualifications Education: BEng in Electrical Engineering, Computer Engineering, Computer Science, or a related discipline. Experience: • Deep knowledge of hardware and digital design fundamentals. • Strong SystemVerilog knowl…
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