astspacemobile · Riga, Latvia
Skills: Python
AST SpaceMobile and our global partners are building the first and only space-based cellular broadband network to be accessible by standard smartphones. Called SpaceMobile, this ultra-powerful network is being designed to provide connectivity at 4G/5G speeds everywhere on the planet – on land, at sea and in flight. Position Overview We are seeking a Senior FPGA Verification Engineer with 6-9 years of experience to design, develop, and execute comprehensive verification strategies for complex FPGA designs. This role requires strong hands-on expertise in SystemVerilog and UVM, testbench architecture, and cross-functional collaboration with design and system teams. Key Responsibilities: Develop and maintain SystemVerilog/UVM-based verification environments for FPGA block-level and top-level designs. Create and execute verification plans, directed and constrained-random test scenarios, assertions, and functional coverage. Perform simulation-based verification of FPGA designs using industry-standard simulators. Drive debug and root-cause analysis of functional issues and work closely with FPGA RTL designers. Integrate and maintain VIPs, scoreboards, checkers, and reference models. Support FPGA bring-up, validation, and debug activities on FPGA platforms and evaluation boards. Review FPGA RTL, verification code, and test plans to ensure quality and completeness. Mentor junior engineers and contribute to FPGA verification best practices. Support regression runs, coverage closure, and release signoff. Qualifications Education: Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or a related field. Experience: 6-9 years of hands-on experience in functional verification. Preferred Qualifications: Familiarity with cadence tools like Xcelium. Familiarity with Xilinx Vivado. Experience with hardware/software co-verification. Knowledge of high-speed interfaces (AXI, AXI‑Stream, DDR, SPI). Soft Skills: Strong analytical and debugging skills.…
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