openai · San Francisco
About the Team OpenAI’s Hardware organization develops AI-native silicon and system-level solutions for the unique demands of advanced AI workloads. The team is developing future generations of AI-native silicon and tightly integrated systems to power the next generation of frontier models. By co-designing chips, systems, tools, and methodologies, the team helps deliver faster, more efficient, and production-ready hardware for OpenAI’s supercomputing platform. About the Role We’re looking for an RTL Design Engineer to help design and develop next-generation AI accelerator silicon. In this role, you'll work across architecture, microarchitecture, and RTL implementation, translating complex system and performance requirements into efficient, scalable hardware designs. You'll collaborate closely with silicon architects, hardware and software engineers, verification, and physical design teams to co-design hardware solutions optimized for demanding AI workloads. This is a hands-on engineering role with opportunities to influence architectural decisions, drive microarchitecture development, and own RTL design from early concept through implementation and integration. We're particularly interested in engineers with experience in Network-on-Chip (NoC), networking, interconnect architectures, or high-performance data movement, though the role encompasses broader RTL design and hardware co-design challenges. In this role, you will: - Design and implement high-performance RTL for next-generation AI accelerator silicon, from microarchitecture definition through implementation and integration. - Collaborate with architecture and software teams to translate system-level requirements into efficient hardware microarchitectures. - Drive hardware/software co-design efforts to optimize performance, power, area, and scalability for AI workloads. - Develop and optimize RTL for complex datapaths, control logic, interconnects, and other critical silicon subsystems. - Evaluate architectura…
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