Astera Labs · San Jose, CA
Skills: Python
Design Verification Engineer – Intern Role overview Astera Labs is seeking a motivated Digital Design Verification Intern to join our San Jose design team. This internship offers hands-on experience in functional verification of high-performance connectivity and networking ASICs. You will work with experienced design and verification engineers to understand design specifications, develop and execute verification tests, debug simulation failures, and help assess the functionality and reliability of complex digital designs. You will collaborate with RTL design, architecture, and other engineering teams throughout the ASIC development process. Key responsibilities Functional verification and test development Assist in developing and executing simulation-based test plans for digital ASIC blocks and subsystems. Develop and maintain test cases using SystemVerilog and other verification languages under the guidance of experienced engineers. Help identify functional scenarios, corner cases, and potential design issues from design specifications. Run simulations and analyze results to verify that RTL behavior meets design requirements. Contribute to test quality, verification efficiency, and functional coverage improvements. Simulation debugging and design quality Debug simulation failures using waveforms, simulation logs, and debugging tools. Work with RTL design engineers to investigate functional issues and help identify root causes. Assist with regression testing and track verification results. Learn and apply verification best practices, including assertions, functional coverage, and systematic debugging. Help maintain verification environments and test documentation. Verification methodology and automation Gain exposure to SystemVerilog-based verification environments and object-oriented programming concepts. Learn Universal Verification Methodology (UVM) and contribute to existing testbenches as appropriate. Assist with reusable verification components, test sequences…
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