Astera Labs · San Jose, CA
Skills: Python
Digital RTL Design Engineer – Intern Role overview Astera Labs is seeking a motivated Digital RTL Design Intern to join our San Jose design team. This internship offers hands-on experience in digital logic design and RTL development for high-performance connectivity and networking ASICs. You will work closely with experienced architects and design engineers to translate design specifications into synthesizable RTL, develop and debug digital logic, and contribute to the design and integration of complex ASICs. You will collaborate with verification, synthesis, physical design, and other cross-functional teams throughout the ASIC development process. Key responsibilities RTL design and implementation Develop and maintain synthesizable Verilog/SystemVerilog RTL for digital ASIC blocks and subsystems under the guidance of experienced engineers. Translate design specifications into digital logic, including datapaths, control logic, finite state machines, counters, register interfaces, and other functional blocks. Implement, modify, and integrate RTL modules following established design and coding guidelines. Participate in RTL code reviews and contribute to design quality, readability, reusability, and maintainability. Debug RTL functionality and assist with resolving design and integration issues. Learn and apply digital design best practices for performance, power, and area optimization. Functional verification and debugging Run RTL simulations and debug functional issues using waveforms, simulation logs, and debugging tools. Work with design verification engineers to understand design requirements and validate RTL functionality. Assist with identifying corner cases and resolving functional issues discovered during simulation. Support RTL lint checks and other design-quality checks. Develop familiarity with verification methodologies, SystemVerilog assertions, and regression-based testing. ASIC design flow and implementation support Gain exposure to the ASIC developmen…
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