Astera Labs · San Jose, CA
Skills: Python
Design Architecture Engineer Intern About the role Astera Labs is seeking a Design Architecture Engineer Intern to help define complex ASIC and system designs from product requirements through implementation. You will work with architects and cross-functional engineering teams to develop clear architectural and microarchitectural specifications, evaluate design tradeoffs, and create the technical foundation for RTL, verification, physical design, DFT, and firmware. You will gain hands-on experience turning system goals into block definitions, interfaces, dataflows, state machines, registers, clocking and reset behavior, performance budgets, and software-programming guidance. You will own a scoped architecture project with mentorship and present the resulting analysis, specification, and recommendations. What you will do Review product requirements, system use cases, protocol specifications, and technical constraints to identify architecture needs and open questions. Develop or update architectural specifications describing major blocks, functions, interfaces, clocking, resets, software interactions, and system behavior. Create or refine microarchitecture specifications for blocks and subsystems, including logical implementation, data structures, programmable registers, state machines, datapaths, and dataflow diagrams. Define and analyze interface behavior, ownership, ordering, buffering, flow control, error handling, interrupts, and recovery sequences. Evaluate architecture tradeoffs involving latency, bandwidth, throughput, buffering, area, power, timing, scalability, complexity, and software impact. Build lightweight performance, capacity, traffic, or resource models using Python, spreadsheets, or comparable tools to support design decisions. Review address maps, CSR/register definitions, configuration options, clock and reset relationships, and programming requirements for consistency and completeness. Trace requirements into implementation and verification consi…
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