Astera Labs · San Jose, CA, United States
Skills: Python
Design Engineer Intern (CCE2) Astera Labs · San Jose, CA · Internship · On-site About Astera Labs Astera Labs builds connectivity solutions that help power modern AI infrastructure. Compute Connectivity Engineering 2 (CCE2) develops complex silicon and connectivity products for high-performance systems, including technologies such as PCIe, CXL, and UALink. The opportunity Join the CCE2 Design Engineering team and gain hands-on experience developing digital logic for advanced connectivity ASICs. You’ll work at the intersection of architecture, RTL, simulation, synthesis, verification, physical design, DFT, and firmware to help turn product requirements into robust, implementable hardware. This internship is designed for someone who enjoys understanding how a system should work, expressing that behavior in RTL, and debugging the difference between intended and observed results. You’ll work with experienced design engineers on a meaningful project involving a block, subsystem, interface, datapath, control path, or reusable design infrastructure. What you’ll do Learn the product architecture, microarchitecture, design methodology, development environment, tools, and project workflow needed to contribute effectively. Read architecture, interface, microarchitecture, and product-requirement documentation and translate requirements into clear design behavior. Design, implement, modify, and document synthesizable RTL in Verilog or SystemVerilog under engineering guidance. Contribute to datapaths, control logic, state machines, register interfaces, configuration and status logic, error handling, arbitration, buffering, or other digital design functions. Work with interface and connectivity logic for technologies such as PCIe, CXL, UALink, Ethernet, SERDES, or related high-speed systems as appropriate for the project. Develop or update design specifications, block diagrams, interface definitions, register descriptions, timing assumptions, and design documentation. Run simulati…
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