Astera Labs · San Jose, CA
Skills: Python
Advanced DV Engineering Intern About the role Astera Labs is seeking an Advanced Design Verification Engineering Intern to help validate complex ASIC and system designs before silicon is available. You will work with design verification engineers to develop tests, improve verification environments, analyze coverage, debug failures, and apply simulation and formal methods to assess whether designs meet their specifications. This internship is intended for a student who is ready to go beyond running existing tests and contribute to verification strategy, reusable infrastructure, and difficult debug problems. You will own a scoped project with guidance from experienced engineers and deliver verification work in a usable state. What you will do Translate architectural, microarchitectural, interface, and product requirements into verification scenarios, test plans, coverage goals, and checkers. Develop and maintain SystemVerilog and UVM testbench components, sequences, tests, monitors, scoreboards, functional coverage, and end-of-test checks. Add directed, constrained-random, error-injection, compliance, stress, and corner-case tests for blocks, subsystems, or top-level functionality. Configure and run simulations and regressions using project submission flows, manifests, plusargs, firmware images, and test definitions. Debug failures by correlating logs, UVM messages, assertions, register reports, firmware output, and Verdi or DVE waveforms. Triage regression failures, distinguish design issues from testbench or environment issues, reproduce failures, and communicate actionable root-cause analysis. Analyze functional and code coverage, identify untested scenarios or coverage gaps, and propose t …truncated… fication, investigate failures systematically, and communicate clear technical conclusions. Strong ownership, curiosity, practical judgment, and willingness to collaborate across engineering functions. Preferred qualifications Experience with UVM components, sequences…
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