Astera Labs · San Jose, CA
Skills: Python
Design Verification Engineer – Intern Role overview Astera Labs is seeking a motivated Digital Design Verification Intern to join our San Jose design team. This internship offers hands-on experience in functional verification of high-performance connectivity and networking ASICs. You will work with experienced design and verification engineers to understand design specifications, develop and execute verification tests, debug simulation failures, and help assess the functionality and reliability of complex digital designs. You will collaborate with RTL design, architecture, and other engineering teams throughout the ASIC development process. Key responsibilities Functional verification and test development Assist in developing and executing simulation-based test plans for digital ASIC blocks and subsystems. Develop and maintain test cases using SystemVerilog and other verification languages under the guidance of experienced engineers. Help identify functional scenarios, corner cases, and potential design issues from design specifications. Exposure to UVM or other constrained-random verification methodologies. Experience with Python, Tcl, Perl, Shell, or other scripting languages for automation. Familiarity with ASIC or FPGA development flows. Exposure to high-speed interfaces or protocols such as PCI Express, Ethernet, AMBA, CXL, NVMe, or other networking and interconnect technologies. Interest in high-performance ASICs, networking, data-center infrastructure, AI accelerators, or cloud computing. Demonstrated ability to learn complex technical concepts and apply them to practical engineering problems. Internship experience and compensation This is a paid, hourly U.S. internship. The applicable hourly rate is determined as part of the offer process and specified in the offer letter, depending on education level ranges form $35/hour to $55/hour. U.S. interns currently receive a $500-per-week housing/relocation stipend for the duration of the internship. Interns partici…
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