Astera Labs · San Jose, CA
Skills: Python
Digital RTL Design Engineer – Intern Role overview Astera Labs is seeking a motivated Digital RTL Design Intern to join our San Jose design team. This internship offers hands-on experience in digital logic design and RTL development for high-performance connectivity and networking ASICs. You will work closely with experienced architects and design engineers to translate design specifications into synthesizable RTL, develop and debug digital logic, and contribute to the design and integration of complex ASICs. You will collaborate with verification, synthesis, physical design, and other cross-functional teams throughout the ASIC development process. Key responsibilities RTL design and implementation Develop and maintain synthesizable Verilog/SystemVerilog RTL for digital ASIC blocks and subsystems under the guidance of experienced engineers. Translate design specifications into digital logic, including datapaths, control logic, finite state machines, counters, register interfaces, and other functional blocks. Implement, modify, and integrate RTL modules following est …truncated… thesis, static timing analysis, or physical design concepts. Familiarity with Python, Tcl, Perl, Shell, or other scripting languages. Exposure to high-speed interfaces or communication protocols such as PCI Express, Ethernet, AMBA, CXL, or other networking and interconnect technologies. Familiarity with verification concepts such as SystemVerilog assertions, UVM, functional coverage, or formal verification. Interest in high-performance ASICs, networking, data-center infrastructure, or AI and cloud computing. Demonstrated ability to learn new technical concepts and apply them to practical engineering problems. Internship experience and compensation This is a paid, hourly U.S. internship. The applicable hourly rate is determined as part of the offer process and specified in the offer letter, depending on education level ranges form $35/hour to $55/hour. U.S. interns currently receive a $500-per…
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