Astera Labs · San Jose, CA
Skills: Python
Digital RTL Design Engineer – NCG Role overview Astera Labs is seeking a motivated Digital RTL Design Engineer to join our San Jose design team. This is an opportunity for a new college graduate to build ownership in digital logic design and RTL development for high-performance connectivity and networking ASICs. You will work with architects and design engineers to translate design specifications into synthesizable RTL, develop and debug digital logic, and contribute to the design and integration of complex ASICs. You will collaborate with verification, synthesis, physical design, DFT, and other cross-functional teams throughout the ASIC development process. As you grow in the role, you will take increasing ownership of RTL quality, implementation readiness, and technical problem-solving. Key responsibilities RTL design and implementation Develop and maintain synthesizable Verilog/SystemVerilog RTL for digital ASIC blocks and subsystems. Translate design specifications into datapaths, control logic, finite state machines, counters, register interfaces, and other functional blocks. Experience with Python, Tcl, Perl, Shell, or other scripting languages. Exposure to high-speed interfaces or communication protocols such as PCI Express, Ethernet, AMBA, CXL, or other networking and interconnect technologies. Familiarity with verification concepts such as SystemVerilog assertions, UVM, functional coverage, or formal verification. Interest in high-performance ASICs, networking, data-center infrastructure, AI accelerators, or cloud computing. Demonstrated ability to learn complex technical concepts, collaborate effectively, and take ownership of engineering results. Compensation The base range for this role is between $150,000 - $170,0000 based on education level. We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of col…
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