Principal Physical Design Engineer, STA at asteralabsasteralabs · San Jose, California, United States

Workplace: On-site

Posted: 2026-10-16

Skills: PythonAstera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Overview As an Astera Labs Principal Physical Design Engineer (STA) you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This role requires end-to-end STA ownership across design stages, deep technical expertise, and close collaboration with RTL, physical design, and verification teams to ensure robust full-chip timing convergence. This role is fully on-site and in-person. Key Responsibilities &l …truncated… ntation, and verification teams to drive timing convergence, providing sign-off level expertise and guidance. Basic Qualifications Bachelor’s in Electrical Engineering or Computer Science required; Master’s preferred. ≥10 years of experience in timing analysis and sign-off for complex SoCs in Server, Storage, or Networking applications. Expertise in timing constraints, STA methodology, and timing closure at both block and full-chip level. Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (7nm or below). Proficiency with Cadence and/or Synopsys physical design/STA to…Sign in to see the original postingBrowse more developer jobs on RoleBurst