asteralabs · San Jose, CA
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is seeking a Senior Principal Digital Design Engineer to drive the architecture and implementation of next-generation digital designs powering AI infrastructure connectivity. This is a high-impact technical leadership role where you'll define micro-architecture strategies for better power, performance and area tradeoff, own complex chip-level design decisions, and guide multiple blocks from concept through silicon bring-up for industry-leading products supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols. As a senior technical leader, you'll shape design met …truncated… t;/ul> Basic Qualifications Bachelor's degree in Electrical Engineering or equivalent 12+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets Demonstrated expertise in architecture definition, micro-architecture development, RTL coding, synthesis, and timing closure Deep knowledge of at least one high-speed protocol: PCIe, CXL, Ethernet, DDR, or similar Production experience with advanced CMOS nodes (≤7nm) Proficiency with Cadence and/or Synopsys digital design flows Track record of delivering multiple high-performance desig…
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